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features description/ordering information SN74LVC821A 10-bit bus-interface flip-flop with 3-state outputs scas304j ? march 1993 ? revised february 2005 operates from 1.65 v to 3.6 v inputs accept voltages to 5.5 v max t pd of 7.3 ns at 3.3 v typical v olp (output ground bounce) <0.8 v at v cc = 3.3 v, t a = 25 c typical v ohv (output v oh undershoot) >2 v at v cc = 3.3 v, t a = 25 c supports mixed-mode signal operation on all ports (5-v input/output voltage with 3.3-v v cc ) i off supports partial-power-down mode operation latch-up performance exceeds 250 ma per jesd 17 esd protection exceeds jesd 22 ? 2000-v human-body model (a114-a) this 10-bit bus-interface flip-flop is designed for 1.65-v to 3.6-v v cc operation. the SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. this device is particularly suitable for implementing wider buffer registers, i/o ports, bidirectional bus drivers with parity, and working registers. the ten flip-flops are edge-triggered d-type flip-flops. on the positive transition of the clock (clk) input, the device provides true data at the q outputs. a buffered output-enable ( oe) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or the high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines significantly. the high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. oe does not affect the internal operations of the latch. previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. ordering information t a package (1) orderable part number top-side marking tube of 25 SN74LVC821Adw soic ? dw lvc821a reel of 2000 SN74LVC821Adwr sop ? ns reel of 2000 SN74LVC821Ansr lvc821a ssop ? db reel of 2000 SN74LVC821Adbr lc821a ?40 c to 85 c tube of 60 SN74LVC821Apw tssop ? pw reel of 2000 SN74LVC821Apwr lc821a reel of 250 SN74LVC821Apwt tvsop ? dgv reel of 2000 SN74LVC821Adgvr lc821a (1) package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 1993?2005, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www .ti.com db, dgv , dw , ns, or pw p ackage (t op view) 12 3 4 5 6 7 8 9 10 1 1 12 2423 22 21 20 19 18 17 16 15 14 13 oe 1d2d 3d 4d 5d 6d 7d 8d 9d 10d gnd v c c 1q2q 3q 4q 5q 6q 7q 8q 9q 10q clk
description/ordering information (continued) SN74LVC821A 10-bit bus-interface flip-flop with 3-state outputs scas304j ? march 1993 ? revised february 2005 inputs can be driven from either 3.3-v or 5-v devices. this feature allows the use of this device as a translator in a mixed 3.3-v/5-v system environment. this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. function table (each flip-flop) inputs output q oe clk d l - h h l - l l l h or l x q 0 h x x z logic diagram (positive logic) 2 www .ti.com 1d oe 1q clk t o nine other channels c1 1d 113 2 23
absolute maximum ratings (1) recommended operating conditions (1) SN74LVC821A 10-bit bus-interface flip-flop with 3-state outputs scas304j ? march 1993 ? revised february 2005 over operating free-air temperature range (unless otherwise noted) min max unit v cc supply voltage range ?0.5 6.5 v v i input voltage range (2) ?0.5 6.5 v v o voltage range applied to any output in the high-impedance or power-off state (2) ?0.5 6.5 v v o voltage range applied to any output in the high or low state (2) (3) ?0.5 v cc + 0.5 v i ik input clamp current v i < 0 ?50 ma i ok output clamp current v o < 0 ?50 ma i o continuous output current 50 ma continuous current through v cc or gnd 100 ma db package 63 dgv package 86 q ja package thermal impedance (4) dw package 46 c/w ns package 65 pw package 88 t stg storage temperature range ?65 150 c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) the value of v cc is provided in the recommended operating conditions table. (4) the package thermal impedance is calculated in accordance with jesd 51-7. min max unit operating 1.65 3.6 v cc supply voltage v data retention only 1.5 v cc = 1.65 v to 1.95 v 0.65 v cc v ih high-level input voltage v cc = 2.3 v to 2.7 v 1.7 v v cc = 2.7 v to 3.6 v 2 v cc = 1.65 v to 1.95 v 0.35 v cc v il low-level input voltage v cc = 2.3 v to 2.7 v 0.7 v v cc = 2.7 v to 3.6 v 0.8 v i input voltage 0 5.5 v high or low state 0 v cc v o output voltage v 3-state 0 5.5 v cc = 1.65 v ?4 v cc = 2.3 v ?8 i oh high-level output current ma v cc = 2.7 v ?12 v cc = 3 v ?24 v cc = 1.65 v 4 v cc = 2.3 v 8 i ol low-level output current ma v cc = 2.7 v 12 v cc = 3 v 24 d t/ d v input transition rise or fall rate 10 ns/v t a operating free-air temperature ?40 85 c (1) all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs, literature number scba004. 3 www .ti.com
electrical characteristics timing requirements SN74LVC821A 10-bit bus-interface flip-flop with 3-state outputs scas304j ? march 1993 ? revised february 2005 over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ (1) max unit i oh = ?100 m a 1.65 v to 3.6 v v cc ? 0.2 i oh = ?4 ma 1.65 v 1.2 i oh = ?8 ma 2.3 v 1.7 v oh v 2.7 v 2.2 i oh = ?12 ma 3 v 2.4 i oh = ?24 ma 3 v 2.2 i ol = 100 m a 1.65 v to 3.6 v 0.2 i ol = 4 ma 1.65 v 0.45 v ol i ol = 8 ma 2.3 v 0.7 v i ol = 12 ma 2.7 v 0.4 i ol = 24 ma 3 v 0.55 i i v i = 0 to 5.5 v 3.6 v 5 m a i off v i or v o = 5.5 v 0 10 m a i oz v o = 0 to 5.5 v 3.6 v 10 m a v i = v cc or gnd 10 i cc i o = 0 3.6 v m a 3.6 v v i 5.5 v (2) 10 d i cc one input at v cc ? 0.6 v, other inputs at v cc or gnd 2.7 v to 3.6 v 500 m a control inputs 5 c i v i = v cc or gnd 3.3 v pf data inputs 4 c o v o = v cc or gnd 3.3 v 7 pf (1) all typical values are at v cc = 3.3 v, t a = 25 c. (2) this applies in the disabled state only. over recommended operating free-air temperature range (unless otherwise noted) (see figure 1) v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 2.7 v 0.15 v 0.2 v 0.3 v unit min max min max min max min max f clock clock frequency (1) (1) 150 150 mhz t w pulse duration, clk high or low (1) (1) 3.3 3.3 ns t su setup time, data before clk (1) (1) 1.9 1.9 ns t h hold time, data after clk (1) (1) 1.5 1.5 ns (1) this information was not available at the time of publication. 4 www .ti.com
switching characteristics operating characteristics SN74LVC821A 10-bit bus-interface flip-flop with 3-state outputs scas304j ? march 1993 ? revised february 2005 over recommended operating free-air temperature range (unless otherwise noted) (see figure 1) v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 2.7 v from to 0.15 v 0.2 v 0.3 v parameter unit (input) (output) min max min max min max min max f max (1) (1) 150 150 mhz t pd clk q (1) (1) (1) (1) 8.5 2.2 7.3 ns t en oe q (1) (1) (1) (1) 8.8 1.3 7.6 ns t dis oe q (1) (1) (1) (1) 6.8 1.6 6.2 ns t sk(o) 1 ns (1) this information was not available at the time of publication. t a = 25 c v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v test parameter unit conditions typ typ typ outputs enabled (1) (1) 65 power dissipation capacitance c pd f = 10 mhz pf per flip-flop outputs disabled (1) (1) 48 (1) this information was not available at the time of publication. 5 www .ti.com
parameter measurement information SN74LVC821A 10-bit bus-interface flip-flop with 3-state outputs scas304j ? march 1993 ? revised february 2005 figure 1. load circuit and voltage waveforms 6 www .ti.com v m t h t s u from output under t est c l (see note a) load circuit s1 v l o a d open gnd r l r l data input t iming input v i 0 vv i 0 v 0 v t w input vol t age w a veforms setup and hold times vol t age w a veforms prop aga tion dela y times inverting and noninverting outputs vol t age w a veforms pulse dura tion t p l h t p h l t p h l t p l h v o h v o h v o l v o l v i 0 v input output w aveform 1 s1 at v l o a d (see note b) output w aveform 2 s1 at gnd (see note b) v o l v o h t p z l t p z h t p l z t p h z v l o a d /2 0 v v o l + v d v o h ? v d 0 v v i vol t age w a veforms enable and disable times low - and high-level enabling outputoutput t p l h /t p h l t p l z /t p z l t p h z /t p z h open v l o a d gnd test s1 notes: a. c l includes probe and jig capacitance. b. w aveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control. w aveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w . d. the outputs are measured one at a time, with one transition per measurement. e. t p l z and t p h z are the same as t d i s . f. t p z l and t p z h are the same as t e n . g. t p l h and t p h l are the same as t p d . h. all parameters and waveforms are not applicable to all devices. output control v m v m v m v m v m v m v m v m v m v m v m v m v i v m v m 1.8 v 0.15 v 2.5 v 0.2 v 2.7 v 3.3 v 0.3 v 1 k w 500 w 500 w 500 w v c c r l 2 v c c 2 v c c 6 v6 v v l o a d c l 30 pf30 pf 50 pf 50 pf 0.15 v0.15 v 0.3 v0.3 v v d v c c v c c 2.7 v2.7 v v i v c c /2 v c c /2 1.5 v1.5 v v m t r /t f 2 ns 2 ns 2.5 ns 2.5 ns inputs
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) SN74LVC821Adble obsolete ssop db 24 tbd call ti call ti SN74LVC821Adbr active ssop db 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Adbre4 active ssop db 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Adbrg4 active ssop db 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Adgvr active tvsop dgv 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Adgvre4 active tvsop dgv 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Adgvrg4 active tvsop dgv 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Adw active soic dw 24 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Adwe4 active soic dw 24 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Adwg4 active soic dw 24 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Adwr active soic dw 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Adwre4 active soic dw 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Adwrg4 active soic dw 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Ansr active so ns 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Ansre4 active so ns 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Ansrg4 active so ns 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Apw active tssop pw 24 60 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Apwe4 active tssop pw 24 60 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Apwg4 active tssop pw 24 60 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Apwle obsolete tssop pw 24 tbd call ti call ti SN74LVC821Apwr active tssop pw 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Apwre4 active tssop pw 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Apwrg4 active tssop pw 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Apwt active tssop pw 24 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Apwte4 active tssop pw 24 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVC821Apwtg4 active tssop pw 24 250 green (rohs & cu nipdau level-1-260c-unlim package option addendum www.ti.com 4-jun-2007 addendum-page 1
orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) no sb/br) (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 4-jun-2007 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant SN74LVC821Adbr ssop db 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 q1 SN74LVC821Adgvr tvsop dgv 24 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 q1 SN74LVC821Adwr soic dw 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 q1 SN74LVC821Ansr so ns 24 2000 330.0 24.4 8.2 15.4 2.5 12.0 24.0 q1 SN74LVC821Apwr tssop pw 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 q1 package materials information www.ti.com 11-mar-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) SN74LVC821Adbr ssop db 24 2000 346.0 346.0 33.0 SN74LVC821Adgvr tvsop dgv 24 2000 346.0 346.0 29.0 SN74LVC821Adwr soic dw 24 2000 346.0 346.0 41.0 SN74LVC821Ansr so ns 24 2000 346.0 346.0 41.0 SN74LVC821Apwr tssop pw 24 2000 346.0 346.0 33.0 package materials information www.ti.com 11-mar-2008 pack materials-page 2
mechanical data msso002e ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 ? 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150
mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153

mechanical data mpds006c february 1996 revised august 2000 post office box 655303 ? dallas, texas 75265 dgv (r-pdso-g**) plastic small-outline 24 pins shown 14 3,70 3,50 4,90 5,10 20 dim pins ** 4073251/e 08/00 1,20 max seating plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 112 24 13 4,30 4,50 0,16 nom gage plane a 7,90 7,70 38 24 16 4,90 5,10 3,70 3,50 a max a min 6,60 6,20 11,20 11,40 56 9,60 9,80 48 0,08 m 0,07 0,40 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. d. falls within jedec: 24/48 pins mo-153 14/16/20/56 pins mo-194

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are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without 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